| CPC G11C 11/412 (2013.01) [H01L 29/6681 (2013.01); H01L 29/7851 (2013.01); H10B 10/12 (2023.02)] | 10 Claims |
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1. A method for forming a layout pattern of a static random access memory (SRAM), at least comprising:
providing a substrate;
forming a plurality of SRAM memory cells, which are arranged on the substrate, wherein each SRAM memory cell comprises:
a plurality of fin structures positioned on the substrate;
a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a portion of the gate structure spanning the fin structure, and the plurality of transistors include: two pull-up transistors (PU), two pull-down transistors (PD), which together form a latch circuit, and two access transistors (PG) connected to the latch circuit;
wherein, in any SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure;
forming a plurality of dummy fin structures on the substrate, comprising:
forming a plurality of mandrel patterns on the substrate;
forming a plurality of spacer patterns to surround each mandrel pattern;
removing each mandrel pattern, leaving each spacer pattern, wherein after forming each spacer pattern, at least one square spacer pattern is located between the PG fin structure and the adjacent PG fin structure.
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