US 12,224,000 B2
Fast, energy efficient 6T SRAM arrays using harvested data
Azeez Bhavnagarwala, Newtown, CT (US)
Assigned to Metis Microsystems, LLC, Newtown, CT (US)
Filed by Metis Microsystems, LLC, Newtown, CT (US)
Filed on May 29, 2022, as Appl. No. 17/827,763.
Claims priority of provisional application 63/248,491, filed on Sep. 26, 2021.
Claims priority of provisional application 63/194,053, filed on May 27, 2021.
Prior Publication US 2023/0042652 A1, Feb. 9, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4094 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A transistor memory device, comprising:
a plurality of transistor storage elements that share a common source or ground terminal, the common source or ground terminal (1) reset to a reference ground potential of the transistor memory device directly before a read data access and a write data access and (2) electrically decoupled from the reference ground potential of the transistor memory device during the read data access and during the write data access.