US 12,223,998 B2
Apparatuses and methods for input receiver circuits and receiver masks for same
Dean D. Gans, Nampa, ID (US); and John D. Porter, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Mar. 15, 2024, as Appl. No. 18/606,198.
Application 17/161,204 is a division of application No. 16/152,306, filed on Oct. 4, 2018, granted, now 10,910,037, issued on Feb. 2, 2021.
Application 18/606,198 is a continuation of application No. 18/312,747, filed on May 5, 2023, granted, now 11,955,162.
Application 18/312,747 is a continuation of application No. 17/161,204, filed on Jan. 28, 2021, granted, now 11,682,447, issued on Jun. 20, 2023.
Prior Publication US 2024/0221818 A1, Jul. 4, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 13/1689 (2013.01); G11C 11/4074 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array;
a command address input circuit configured to receive a command address signal, the command address input circuit comprising a command address input receiver configured to capture an input command address signal that is based at least in part on a predefined receiver mask, wherein the receiver mask has a first timing parameter associated with a first voltage level and further has a second timing parameter associated with a second voltage level, wherein the second timing parameter is greater than the first timing parameter, wherein the predefined receiver mask has a hexagonal shape; and
an external clock terminal configured to receive a clock signal, wherein a center of the receiver mask is at a cross point of the clock signal.