US 12,223,997 B2
Nonvolatile semiconductor memory device
Toshifumi Watanabe, Yokohama Kanagawa (JP); and Naofumi Abiko, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Oct. 19, 2023, as Appl. No. 18/490,148.
Application 18/490,148 is a continuation of application No. 17/873,427, filed on Jul. 26, 2022, granted, now 11,842,759.
Application 17/873,427 is a continuation of application No. 17/222,969, filed on Apr. 5, 2021, granted, now 11,430,502, issued on Aug. 30, 2022.
Application 17/222,969 is a continuation of application No. 16/799,402, filed on Feb. 24, 2020, granted, now 11,024,360, issued on Jun. 1, 2021.
Claims priority of application No. 2019-156008 (JP), filed on Aug. 28, 2019.
Prior Publication US 2024/0046974 A1, Feb. 8, 2024
Int. Cl. G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/56 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 16/04 (2006.01)
CPC G11C 11/4074 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G06F 3/0688 (2013.01); G06F 11/1072 (2013.01); G11C 5/147 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 16/0483 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell;
a word line connected to a gate of the memory cell;
a bit line connected to the memory cell;
a first transistor connected to the bit line; and
a control circuit configured to perform a read operation on the memory cell,
wherein the control circuit is configured to, during the read operation,
apply to the word line a first voltage, then a second voltage greater than the first voltage at a first timing, and then a third voltage smaller than the second voltage at a second timing after the first timing, and
apply to a gate of the first transistor a fourth voltage, then a fifth voltage at a third timing after the first timing and before the second timing, and then a sixth voltage that is higher than the fourth voltage and lower than the fifth voltage at a fourth timing after the second timing.