US 12,223,996 B2
Address selection circuit and control method thereof, and memory
Xianlei Cao, Hefei (CN); and Xian Fan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 13, 2023, as Appl. No. 18/154,256.
Claims priority of application No. 202210287583.5 (CN), filed on Mar. 23, 2022.
Prior Publication US 2023/0326512 A1, Oct. 12, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4087 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An address selection circuit, comprising:
an address receiving circuit comprising:
a refresh address generator configured to generate a regular refresh address signal; and
a first selector configured to receive the regular refresh address signal, an active address signal, and a first selection signal and configured to: output the active address signal during a period when the first selection signal indicates an active state and output the regular refresh address signal during a period when the first selection signal indicates a refresh state;
a row hammer address generation circuit connected to the address receiving circuit and configured to: generate a second address output signal and a row hammer address redundancy identifier according to a received first selection signal, an actual active address signal, and the first address output signal; and
a decoding circuit connected to the row hammer address generation circuit and configured to: generate a target address and the actual active address signal according to a received second address output signal and the row hammer address redundancy identifier;
wherein the row hammer address generation circuit comprises:
a row hammer address generator configured to: receive the first selection signal and the actual active address signal, and generate a row hammer address signal and the row hammer address redundancy identifier according to the actual active address signal during the period when the first selection signal indicates the active state; and
a second selector configured to receive a second selection signal and connect to an output terminal of the row hammer address generator and an output terminal of the first selector and configured to: sequentially receive and output the first address output signal as the second address output signal before receiving the second selection signal; stop outputting the first address output signal when receiving the second selection signal, receive and output the row hammer address signal as the second address output signal, and output the row hammer address redundancy identifier; and resume receiving and outputting the first address output signal as the second address output signal after outputting the row hammer address signal.