US 12,223,995 B2
Adaptive memory registers
John Christopher Sancon, Boise, ID (US); Kang-Yong Kim, Boise, ID (US); Yang Lu, Boise, ID (US); and Hyun Yoo Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/823,407.
Prior Publication US 2024/0071461 A1, Feb. 29, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4096 (2013.01)] 55 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array;
a refresh counter configured to store at least a portion of an address indicative of a refresh operation for a row of the memory array;
at least one memory register; and
logic configured to:
access the refresh counter;
write values to respective entries of the at least one memory register, the values representing the at least a portion of the address; and
write other values to respective entries of the at least one memory register, the other values representing at least a portion of another address indicative of another refresh operation for another row of the memory array, based on a determination that the refresh counter has incremented.