US 12,223,926 B2
Data integrated circuit including latch controlled by clock signals and display device including the same
Wontae Kim, Cheongju-si (KR); Sooyeon Kim, Seoul (KR); Young-Il Ban, Hwaseong-si (KR); and Sunkyu Son, Suwon-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Oct. 27, 2022, as Appl. No. 18/050,080.
Application 18/050,080 is a continuation of application No. 16/794,787, filed on Feb. 19, 2020, granted, now 11,488,560.
Application 16/794,787 is a continuation of application No. 14/863,929, filed on Sep. 24, 2015, abandoned.
Claims priority of application No. 10-2015-0032720 (KR), filed on Mar. 9, 2015.
Prior Publication US 2023/0075010 A1, Mar. 9, 2023
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3688 (2013.01) [G09G 3/3611 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01); G09G 2370/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A display device comprising:
a display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels;
a data driving circuit configured to output a plurality of data voltages to the plurality of data lines in response to a data control signal;
a gate driving circuit configured to output a plurality of gate signals to the plurality of gate lines in response to a gate control signal; and
a timing controller configured to output the data control signal and the gate control signal,
wherein the data control signal includes a main clock signal and a clock signal,
wherein the data driving circuit comprising a plurality of data integrated circuits, each of the plurality of data integrated circuits comprises:
a shift register configured to receive the clock signal from the timing controller and output a plurality of latch clock signals that are sequentially activated in response to the clock signal;
a latch circuit configured to latch a plurality of image signals from the timing controller in response to the plurality of latch clock signals from the shift register and output a plurality of digital image signals in response to a plurality of latch output signals;
an output circuit configured to convert the plurality of digital image signals to the plurality of data voltages; and
a clock generator configured to receive the main clock signal, divide the main clock signal to generate the plurality of latch output signals and output the plurality of latch output signals,
wherein the latch circuit comprises:
a first latch group configured to receive a first subset of the image signals, a first subset of the latch clock signals and a first latch output signal from among the plurality of latch output signals, latch the first subset of the image signals based on the first subset of the latch clock signals and output a plurality of first digital image signals of the plurality of digital image signals in response to the first latch output signal; and
a second latch group configured to receive a second subset of the image signals, a second subset of the latch clock signals and a second latch output signal from among the plurality of latch output signals, latch the second subset of the image signals based on the second subset of the latch clock signals and output a plurality of second digital image signals of the plurality of digital image signals in response to the second latch output signal among the plurality of latch output signals, and
wherein an active portion of the first latch output signal is not overlapped with an active portion of the second latch output signal.