US 12,223,905 B2
Display panel and display apparatus
Uijong Song, Suwon-si (KR); Sunkwon Kim, Suwon-si (KR); Hyungjoong Kim, Suwon-si (KR); Seongyoung Ryu, Suwon-si (KR); Yilho Lee, Suwon-si (KR); and Heejin Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 28, 2024, as Appl. No. 18/590,365.
Claims priority of application No. 10-2023-0039188 (KR), filed on Mar. 24, 2023; application No. 10-2023-0064985 (KR), filed on May 19, 2023; and application No. 10-2023-0064986 (KR), filed on May 19, 2023.
Prior Publication US 2024/0321206 A1, Sep. 26, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10K 59/131 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); H10K 59/131 (2023.02); G09G 2300/0814 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a plurality of pixels arranged in rows and columns;
a scan driver connected with the rows of pixels through a scan line, a first emission control line, a second emission control line, and a read-out/initialization control line;
a data driver connected with the columns of pixels through a data line; and
a read-out circuit connected with the columns of pixels through a read-out line and configured to read out an electrical characteristic of each of the plurality of pixels,
wherein each of the plurality of pixels comprises:
a first transistor including a first electrode connected with a first node, a second electrode connected with a third node, and a gate connected with a second node;
a second transistor including a first electrode connected with the data line, a second electrode connected with the first node, and a gate connected with the scan line;
a third transistor including a first electrode connected with the second node, a second electrode connected with the third node, and a gate connected with the scan line;
a fourth transistor including a first electrode connected with a power node to which a source voltage is supplied, a second electrode connected with the first node, and a gate connected with the first emission control line;
a fifth transistor including a first electrode, a second electrode, and a gate, the first electrode of the fifth transistor being connected with the third node and the gate of the fifth transistor being connected with the second emission control line;
a sixth transistor including a first electrode connected with the read-out line, a second electrode connected with the third node, and a gate connected with the read-out/initialization control line;
a capacitor connected between the first node and the second node; and
an organic light-emitting diode connected between the second electrode of the fifth transistor and a ground node to which a ground voltage is supplied.