US 12,223,898 B2
Pixel circuit optimizing a current flow and display apparatus comprising the pixel circuit
DaeKyu Kim, Gyeonggi-do (KR); DaeSung Jung, Gyeonggi-do (KR); and JeongHo Kim, Gyeonggi-do (KR)
Assigned to LG DISPLAY CO., LTD., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on May 25, 2023, as Appl. No. 18/202,064.
Claims priority of application No. 10-2022-0066725 (KR), filed on May 31, 2022.
Prior Publication US 2023/0386407 A1, Nov. 30, 2023
Int. Cl. G09G 3/3233 (2016.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H10K 77/10 (2023.01); H10K 102/00 (2023.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 77/111 (2023.02); H10K 2102/311 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A pixel circuit comprising:
a capacitor connected between a first node and a second node;
a first transistor connected between a data line and the first node;
a driving transistor including a gate electrode connected to the second node, a first electrode connected to a first voltage supply line, and a second electrode connected to a third node;
a second transistor connected between the second node and a fourth node, the fourth node being connected to a reference voltage supply line;
a third transistor connected between the fourth node and a fifth node;
a fourth transistor connected between the third node and the fifth node;
a fifth transistor connected between the second node and the third node; and
an emission element connected to the driving transistor and connected to the third transistor through the fifth node,
wherein a first scan signal for being applied with the first transistor is different from a second scan signal for being applied with the fifth transistor, and
wherein a turn-on period of the fifth transistor is longer than a turn-on period of the first transistor.