| CPC G09G 3/32 (2013.01) [G11C 19/287 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] | 12 Claims |

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1. A gate drive circuit, wherein the gate drive circuit comprises one or more shift register groups, each of the shift register groups comprises N adjacent shift registers that output in sequence, N being an integer greater than or equal to 3, each of the shift registers comprises:
a first output stage configured to output a gate drive signal;
a frequency division control module configured to control outputting of the gate drive signal based on a refresh frequency,
wherein a control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.
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