| CPC G09G 3/30 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01)] | 18 Claims |
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1. A gate driver comprising:
an output clock line through which an output clock signal is applied;
a dummy clock line disposed adjacent to the output clock line and through which a dummy clock signal is applied;
a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output; and
a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied,
wherein the output clock line and the dummy clock line are disposed on different layers from each other,
wherein the output clock line is disposed on a first layer,
wherein the dummy clock line is disposed on a second layer located below the first layer; and
wherein the pull-up transistor and the pull-down transistor are disposed on a third layer located below the second layer.
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