US 12,223,682 B2
Variable width interleaved coding for graphics processing
Stephen Junkins, Bend, OR (US); Sreenivas Kothandaraman, Sammamish, WA (US); Prasoonkumar Surti, Folsom, CA (US); Srihari Pratapa, Seattle, WA (US); William Hux, Hillsboro, OR (US); and John Feit, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,038.
Claims priority of provisional application 63/163,685, filed on Mar. 19, 2021.
Prior Publication US 2022/0301228 A1, Sep. 22, 2022
Int. Cl. G06T 9/00 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 9/00 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors including a graphic processor; and
memory for storage of data including data for graphics processing;
wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to:
receive a plurality of bitstreams from a plurality of workgroups;
perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups;
perform variable interleaving of the bitstreams for each workgroup of the plurality of workgroups, wherein a number of data elements that are interleaved for each workgroup in each of a plurality of iterations is based at least in part on current data requirements for decoding for each workgroup received from the decoder pipeline; and
compact interleaved bitstream outputs for each of the plurality of workgroups into a contiguous stream of interleaved data.