US 12,223,572 B2
Separately processing regions or objects of interest from a render engine to a display engine or a display panel
Joydeep Ray, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 13, 2023, as Appl. No. 18/299,748.
Application 18/299,748 is a continuation of application No. 17/524,130, filed on Nov. 11, 2021, granted, now 11,699,254.
Application 17/524,130 is a continuation of application No. 16/690,581, filed on Nov. 21, 2019, granted, now 11,200,717, issued on Dec. 14, 2021.
Application 16/690,581 is a continuation of application No. 15/494,594, filed on Apr. 24, 2017, granted, now 10,504,259, issued on Dec. 10, 2019.
Prior Publication US 2023/0281898 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 11/60 (2006.01); G06F 3/14 (2006.01); G06T 1/20 (2006.01); G06T 7/254 (2017.01); G06T 15/00 (2011.01); G09G 5/39 (2006.01); G09G 5/00 (2006.01)
CPC G06T 11/60 (2013.01) [G06F 3/1438 (2013.01); G06T 1/20 (2013.01); G06T 7/254 (2017.01); G06T 15/00 (2013.01); G06T 15/005 (2013.01); G09G 5/39 (2013.01); G06T 2200/28 (2013.01); G09G 5/001 (2013.01); G09G 2340/0435 (2013.01); G09G 2352/00 (2013.01); G09G 2360/06 (2013.01); G09G 2360/08 (2013.01); G09G 2360/121 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A graphics processing unit, comprising:
a plurality of texture units,
a shared memory coupled to the plurality of texture units,
a plurality of register files coupled to the shared memory,
a plurality of load/store units coupled to the shared memory, and
a plurality of graphics processing cores coupled to the plurality of register files, wherein at least some of the plurality of graphics processing cores are to:
receive a workload prepared by a virtual reality application;
render, in a rendering engine, the workload, comprising to render a plurality of frames, the rendering engine to render at least some of the plurality of frames comprising separate surfaces, including to pixel shade a first region of the at least some of the plurality of frames at a first shading rate and to pixel shade a second region of the at least some of the plurality of frames at a second shading rate that is twice the first shading rate;
provide the plurality of frames to a display engine;
determine whether a display panel is capable of buffering display surfaces separately;
in response to determining that the display panel is not capable of buffering the display surfaces separately, combine the separate surfaces of the at least some of the plurality of frames in the display engine; and
send the plurality of frames to the display panel.