US 12,223,560 B2
Clock architecture and method supporting PCIE clock, and medium
Haibo Wang, Jiangsu (CN); and Zhihua Ge, Jiangsu (CN)
Assigned to SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 18/570,597
Filed by SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Jun. 7, 2022, PCT No. PCT/CN2022/097425
§ 371(c)(1), (2) Date Dec. 14, 2023,
PCT Pub. No. WO2023/115834, PCT Pub. Date Jun. 29, 2023.
Claims priority of application No. 202111585044.1 (CN), filed on Dec. 23, 2021.
Prior Publication US 2024/0273668 A1, Aug. 15, 2024
Int. Cl. G06T 1/20 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 13/4022 (2013.01); G06F 13/4291 (2013.01); G06F 2213/0026 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A clock architecture supporting a PCIE clock, comprising: a controller, a graphics processing unit (GPU), a programmable communication interface extension (PCIE) switch, a field-programmable gate array (FPGA), a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device;
wherein the first clock generator is connected to the first clock fan-out device, and is configured to generate a 100 MHz homologous clock signal; the first clock fan-out device is connected to the controller and the FPGA, and is configured to fan out the 100 MHz homologous clock signal; and
the second clock generator is connected to the second clock fan-out device, and is configured to generate a 100 MHz non-homologous clock signal; the second clock fan-out device is connected to the FPGA, and is configured to fan out the 100 MHz non-homologous clock signal; the controller is connected to the PCIE switch, the PCIE switch is connected to the GPU;
the FPGA is connected to the PCIE switch and the GPU, and is configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, wherein the clock architecture modes are a homologous mode and a non-homologous mode;
wherein the FPGA is further configured to:
acquire the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquire the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode; and
acquire the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.