US 12,223,546 B2
Systems and methods for coordinating processing of scheduled instructions across multiple components
Zachary Bonig, Skokie, IL (US); Eric Thill, Naperville, IL (US); Pearce Peck-Walden, Chicago, IL (US); José Antonio Acuña-Rohter, Chicago, IL (US); Barry Galster, Chicago, IL (US); Neil Steuber, Evanston, IL (US); James Bailey, Hanover Park, IL (US); and Jake Siddall, Chicago, IL (US)
Assigned to Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed by Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed on Dec. 7, 2023, as Appl. No. 18/532,122.
Application 18/532,122 is a continuation of application No. 17/672,207, filed on Feb. 15, 2022, granted, now 11,875,404.
Application 17/672,207 is a continuation of application No. 16/925,751, filed on Jul. 10, 2020, granted, now 11,288,744, issued on Mar. 29, 2022.
Application 16/925,751 is a continuation of application No. 15/232,208, filed on Aug. 9, 2016, granted, now 10,748,210, issued on Aug. 18, 2020.
Prior Publication US 2024/0104657 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 40/04 (2012.01); G06Q 10/1093 (2023.01)
CPC G06Q 40/04 (2013.01) [G06Q 10/1093 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A computer implemented method comprising:
receiving, by each of a plurality of independently operating processors from one or more receivers coupled therewith, a data message comprising signal data, wherein each processor is coupled with a memory in which at least one instruction has been previously stored in association with one of a plurality of different signal data; and
determining, by each of the plurality of processors, that the signal data of the received data message corresponds with the signal data associated with one of the stored at least one instruction stored in the memory coupled therewith, and based thereon processing the corresponding one of the stored at least one instruction.