US 12,223,436 B2
Processor compiler for scheduling instructions to reduce execution delay due to dependencies
Jonathan Alexander Ross, Palo Alto, CA (US); and Gregory M. Thorson, Palo Alto, CA (US)
Assigned to GROQ, INC., Mountain View, CA (US)
Filed by Groq, Inc., Mountain View, CA (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,203.
Application 18/405,203 is a continuation of application No. 18/083,388, filed on Dec. 16, 2022, granted, now 11,868,908.
Application 18/083,388 is a continuation of application No. 16/526,936, filed on Jul. 30, 2019, granted, now 11,568,275, issued on Jan. 31, 2023.
Application 16/526,936 is a continuation of application No. 16/132,102, filed on Sep. 14, 2018, granted, now 11,170,307, issued on Nov. 9, 2021.
Claims priority of provisional application 62/561,516, filed on Sep. 21, 2017.
Prior Publication US 2024/0144044 A1, May 2, 2024
Int. Cl. G06N 5/022 (2023.01); G06N 20/00 (2019.01)
CPC G06N 5/022 (2013.01) [G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining, by a compiler, a processor selected from a plurality of processors for executing an instruction based on availability of at least a first resource;
selecting, by the compiler, a memory location for storing operands of the instruction based on the processor that is determined to execute the instruction, the memory location selected to reduce an access delay by the processor of the operands from the memory location during execution of the instruction by the first resource, the memory location indicating a physical memory address within a memory unit associated with the processor; and
compiling, by the compiler, a plurality of compiled binaries from a single predictive model.