US 12,223,413 B2
Methods and apparatus to tile walk a tensor for convolution operations
Yaniv Fais, Tel Aviv TA (IL); and Moshe Maor, Kiryat Mozking Z (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2023, as Appl. No. 18/392,761.
Application 18/392,761 is a continuation of application No. 17/954,846, filed on Sep. 28, 2022, granted, now 12,112,251.
Application 17/954,846 is a continuation of application No. 16/540,581, filed on Aug. 14, 2019, granted, now 11,494,608.
Prior Publication US 2024/0119255 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/448 (2018.01); G06F 8/41 (2018.01); G06F 17/15 (2006.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01)
CPC G06N 3/04 (2013.01) [G06F 8/41 (2013.01); G06F 17/15 (2013.01); G06N 3/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
partitioning an input tensor of a convolution of a neural network into tiles;
partitioning a tile into a plurality of micro-tiles;
performing an iteration of the convolution on the tile, wherein performing the iteration of the convolution comprises:
performing, by a group of convolution engines, multiply-accumulate (MAC) operations on the plurality of micro-tiles of the tile in parallel, different micro-tiles processed by different convolution engines in the group; and
generating an output tensor of the convolution based on the iteration of the convolution.