US 12,223,353 B2
Systems and methods for synchronization of multi-thread lanes
Valentin Andrei, San Jose, CA (US); Subramaniam Maiyuran, Gold River, CA (US); SungYe Kim, Folsom, CA (US); Varghese George, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); and Aravindh Anantaraman, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 5, 2023, as Appl. No. 18/481,489.
Application 18/481,489 is a continuation of application No. 16/355,187, filed on Mar. 15, 2019, granted, now 11,816,500.
Prior Publication US 2024/0103910 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/48 (2006.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 15/80 (2006.01); G06T 1/20 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 9/38 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08); G06F 9/52 (2013.01); G06F 15/8007 (2013.01); G06T 1/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A graphics multiprocessor, comprising: a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types; and
a regroup circuitry to regroup threads from the initial state of groups of first and second groups into a regrouped state of groups including a third group having threads of the first instruction type and a fourth group having threads of the second instruction type based on an instruction type and to determine an order of inserting the third group and the fourth group into the queue to minimize divergence between threads.