| CPC G06F 9/3877 (2013.01) [G06F 15/7821 (2013.01); G11C 7/06 (2013.01); G11C 7/065 (2013.01); G11C 7/1006 (2013.01); G11C 7/1036 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |

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1. A processor in memory (PIM) apparatus comprising:
a memory device configured to receive a first plurality of mathematical operations of first control flow instructions and a second plurality of mathematical operations of second control flow instructions generated by a host, including:
a first array of memory cells;
a second array of memory cells;
a first execution unit, coupled to the first array, to execute the first control flow instructions;
a second execution unit, coupled to the second array, to execute the second control flow instructions;
a first controller configured to control an execution of the first control flow instructions on data stored in the first array using the first execution unit; and
a second controller configured to control an execution of the second control flow instructions on data stored in the second array using the second execution unit.
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