US 12,223,327 B2
CPUs with capture queues to save and restore intermediate results and out-of-order results
Timothy D. Anderson, University Park, TX (US); Duc Bui, Grand Prairie, TX (US); Joseph Zbiciak, San Jose, CA (US); and Reid E. Tatge, Los Altos, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 16, 2023, as Appl. No. 18/487,186.
Application 18/487,186 is a continuation of application No. 17/688,260, filed on Mar. 7, 2022, granted, now 11,789,742.
Application 17/688,260 is a continuation of application No. 16/685,747, filed on Nov. 15, 2019, granted, now 11,269,650, issued on Mar. 8, 2022.
Claims priority of provisional application 62/786,374, filed on Dec. 29, 2018.
Prior Publication US 2024/0036876 A1, Feb. 1, 2024
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3867 (2013.01) [G06F 9/3838 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A method comprising:
beginning execution of a first instruction and a second instruction by a processor;
determining that the first instruction and the second instruction both write to a memory location and that a result of the second instruction will be produced for writing to the memory location prior to completion of the first instruction;
based on the determination:
storing the result of the second instruction in a first memory; and
after completion of the first instruction, storing the result of the second instruction at the memory location; and
storing an intermediate result of a third instruction in the first memory.