US 12,223,324 B2
Methods and apparatus for providing mask register optimization for vector operations
Michael Estlick, Fort Collins, CO (US); Eric Dixon, Fort Collins, CO (US); Theodore Carlson, Fort Collins, CO (US); and Erik D. Swanson, Fort Collins, CO (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,604.
Prior Publication US 2024/0111526 A1, Apr. 4, 2024
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3836 (2013.01) [G06F 9/3824 (2013.01); G06F 9/30036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a vector data processing unit comprising:
a shared scheduler queue configured to store in a same queue, at least one entry that includes at least one mask type instruction and another entry that includes at least one vector type instruction, wherein the at least one mask type instruction and the at least one vector type instruction each comprise a source operand having a corresponding shared source register bit field that provides access to a shared register space; and
shared pipeline control circuitry operative to control either of a vector data path or a mask data path, based on a type of instruction picked from the shared scheduler queue.