| CPC G06F 9/3001 (2013.01) [G06F 9/30029 (2013.01); G06F 9/3004 (2013.01)] | 28 Claims |

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1. A method of operating a processor having an associated memory, the method comprising:
applying first combinational, arithmetic or combinational and arithmetic operations to obtained data and an expected value, the applying the first combinational, arithmetic or combinational and arithmetic operations generating a plurality of result bit sequences, wherein when the value of the obtained data corresponds to the expected value, values of generated plurality of result bit sequences are different from each other and correspond to expected values of the result bit sequences;
applying second combinational, arithmetic or combinational and arithmetic operations to a first memory address, a second memory address, and the plurality of result bit sequences, the applying the second combinational, arithmetic or combinational and arithmetic operations generating a memory address, wherein,
when the values of the generated plurality of result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address, and
when one or more values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address;
jumping to the generated memory address; and
executing a software routine stored in an area of the memory starting at the generated memory address.
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