US 12,223,318 B2
Apparatus and method for managing unsupported instruction set architecture (ISA) features in a virtualized environment
Tyler Sondag, Beaverton, OR (US); David Sheffield, Portland, OR (US); and Sofia Pediaditaki, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,572.
Prior Publication US 2022/0308867 A1, Sep. 29, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/22 (2006.01); G06F 9/455 (2018.01)
CPC G06F 9/223 (2013.01) [G06F 9/30174 (2013.01); G06F 9/455 (2013.01); G06F 9/45558 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture;
at least one core of the plurality of cores comprising:
a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions;
execution circuitry to execute the corresponding microoperations;
wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine,
wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and
wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support.