US 12,223,301 B2
Generating source code adapted for implementation on FPGAs
Joerg Niere, Paderborn (DE); Kingshuk Karuri, Paderborn (DE); and Pubali Mazumder, Paderborn (DE)
Assigned to DSPACE GMBH, Paderborn (DE)
Filed by dSPACE GmbH, Paderborn (DE)
Filed on Mar. 17, 2023, as Appl. No. 18/185,413.
Prior Publication US 2024/0311112 A1, Sep. 19, 2024
Int. Cl. G06F 8/41 (2018.01)
CPC G06F 8/456 (2013.01) [G06F 8/4441 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for generating source code from one or more blocks of a block diagram that comprises at least two blocks, including a source block emitting a matrix signal corresponding to an array variable and an operation block receiving the matrix signal and emitting an output signal based on an operation applied to the matrix signal, the method comprising:
transforming the block diagram into an intermediate representation, wherein transforming the block diagram into the intermediate representation comprises transforming the at least two blocks, and wherein at least one loop results from transforming the operation block;
identifying at least one candidate loop in the intermediate representation, wherein a loop body of the at least one candidate loop comprises at least one instruction that accesses the array variable;
identifying at least one parallelizable loop from the at least one candidate loop;
determining a build option for the at least one parallelizable loop;
determining a build option for the array variable;
inserting build pragmas based on the determined build options in the intermediate representation; and
translating the intermediate representation into the source code.