US 12,223,250 B2
Method of manufacturing integrated circuit having through-substrate via
Chih-Chia Hu, Taipei (TW); Ming-Fa Chen, Taichung (TW); Sen-Bor Jan, Tainan (TW); and Meng-Wei Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 11, 2023, as Appl. No. 18/350,738.
Application 18/350,738 is a continuation of application No. 17/366,021, filed on Jul. 1, 2021, granted, now 11,748,544.
Application 17/366,021 is a continuation of application No. 16/924,195, filed on Jul. 9, 2020, granted, now 11,080,455, issued on Aug. 3, 2021.
Prior Publication US 2023/0351086 A1, Nov. 2, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 119/06 (2020.01); H01L 23/48 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01)
CPC G06F 30/392 (2020.01) [G06F 2119/06 (2020.01); H01L 23/481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating an integrated circuit (IC) layout design, comprising:
generating a pattern of a through-substrate via (TSV) region in a keep-out-zone (KOZ);
generating a pattern of first channel regions of first transistors in a layout region surrounding the KOZ;
generating a pattern of second channel regions of second transistors in the KOZ, wherein the first channel regions of the first transistors and the second channel regions of the second transistors are spaced apart from the TSV region, and the second channel regions of the second transistors are substantially identical in channel width; and
manufacturing an IC based on the IC layout design.