US 12,223,247 B2
Logic cell structures and related methods
Kumar Lalgudi, Fremont, CA (US); Ranjith Kumar, Hsinchu (TW); Mohammed Rabiul Islam, Austin, TX (US); and Jianyang Xu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Sep. 22, 2023, as Appl. No. 18/472,280.
Application 18/472,280 is a division of application No. 17/232,525, filed on Apr. 16, 2021, granted, now 11,816,412.
Prior Publication US 2024/0012975 A1, Jan. 11, 2024
Int. Cl. G06F 30/367 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/367 (2020.01) [G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/337 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of making an integrated circuit structure, the method comprising:
addressing a timing condition of a logic cell having a plurality of inputs by allocating a current-driving capability of the logic cell unequally among the plurality of inputs without substantially changing a size of the logic cell.