US 12,223,246 B2
Systems, methods, and computer program products for transistor compact modeling using artificial neural networks
Jing Wang, San Jose, CA (US); and Woosung Choi, Milpitas, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 2, 2021, as Appl. No. 17/465,361.
Claims priority of provisional application 63/091,067, filed on Oct. 13, 2020.
Prior Publication US 2022/0114317 A1, Apr. 14, 2022
Int. Cl. G06F 30/367 (2020.01); G06N 3/08 (2023.01); G06F 119/02 (2020.01)
CPC G06F 30/367 (2020.01) [G06N 3/08 (2013.01); G06F 2119/02 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer implemented method for analyzing performance of a semiconductor device, the method comprising:
providing training data comprising input state values and training capacitance values to a neural network executing on a computer system;
processing the input state values through the neural network to generate modeled charge values;
converting the modeled charge values to modeled capacitance values;
determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values;
in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network;
using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output;
determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory; and
in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network.