US 12,223,211 B2
Enhanced input of machine-learning accelerator activations
Lukasz Lew, Sunnyvale, CA (US); and Wren Romano, Mountain View, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Sep. 15, 2023, as Appl. No. 18/468,630.
Application 18/468,630 is a continuation of application No. 17/738,403, filed on May 6, 2022, granted, now 11,762,602.
Application 17/738,403 is a continuation of application No. 16/718,055, filed on Dec. 17, 2019, granted, now 11,327,690, issued on May 10, 2022.
Claims priority of provisional application 62/935,038, filed on Nov. 13, 2019.
Prior Publication US 2024/0192897 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06N 20/00 (2019.01)
CPC G06F 3/0679 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 9/30036 (2013.01); G06F 9/50 (2013.01); G06N 20/00 (2019.01)] 10 Claims
OG exemplary drawing
 
1. A method performed using a processor comprising a plurality of activation lines and a plurality of delay registers, wherein each delay register is paired with a respective activation line, the method comprising:
on a first global tick, populating a first delay register with a first activation value from a first activation line of the processor, and
routing a second activation value to the first activation line;
on a first local tick of the first global tick, providing at least the first activation value from the delay register to a compute tile of the processor; and
on each subsequent local tick of the first global tick, providing one or more additional activation values from the plurality of activation lines after providing at least the first activation value from the delay register.