US 12,223,208 B2
Enhanced write performance utilizing program interleave
Daniel J. Hubbard, Boise, ID (US); and Roy Leonard, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 20, 2023, as Appl. No. 18/513,742.
Application 18/513,742 is a continuation of application No. 17/727,131, filed on Apr. 22, 2022, granted, now 11,875,061.
Prior Publication US 2024/0086115 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/0846 (2016.01); G06F 12/0882 (2016.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 12/0851 (2013.01); G06F 12/0882 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
a processing device, operatively coupled with memory, to perform operations comprising:
initiating a write operation to write data to a first multiple level cell (XLC) storage comprising a first XLC block and a second XLC storage comprising a second XLC block; and
causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave, wherein the first number of pages and the second number of pages are defined by an interleave mix comprising an interleave ratio between a first XLC write mode and a second XLC write mode.