US 12,223,204 B2
Memory-aligned access operations
Luca Porzio, Casalnuovo (IT); Dionisio Minopoli, Frattamaggiore (IT); and Olivier Duval, Pacifica, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 13, 2022, as Appl. No. 18/080,568.
Claims priority of provisional application 63/291,769, filed on Dec. 20, 2021.
Prior Publication US 2023/0195387 A1, Jun. 22, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device comprising a plurality of physical pages of non-volatile memory cells; and
a controller coupled with the memory device and configured to cause the apparatus to:
transmit, to a host system, an indication of a data size corresponding to a quantity of physical pages that are addressable by individual first-level pages of a first-level page table for mapping logical addresses to respective physical pages of the plurality of physical pages, wherein a target packet size for an application at the host system is based at least in part on the data size;
receive, from the host system based at least in part on transmitting the indication, a set of data associated with the application and a command to write the set of data to the memory device, a size of the set of data being the target packet size and the command comprising a logical address for the set of data;
identify, based at least in part on the logical address, a second-level entry of a second-level page table, wherein the second-level entry of the second-level page table points to a first-level page of the first-level page table, and wherein first-level entries of the first-level page map a set of logical addresses to a set of physical addresses, the set of logical addresses comprising the logical address; and
write, based at least in part on identifying the second-level entry, the set of data to the set of physical addresses beginning at a first physical address corresponding to a lowest logical address mapped to by a lowest level page of the first-level page table and ending at a second physical address corresponding to a highest logical address mapped to by the lowest level page of the first-level page table.