| CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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16. A method, comprising:
generating a memory access request by a first processing tile of a plurality of processing tiles that are fabricated within a processor die, wherein the processor die and at least one memory die comprise a die stack with at least one memory tile of a plurality of memory tiles fabricated within each memory die stacked with each processing tile to provide local memory for the processing tile;
translating, by a mapping circuit within the first processing tile, an address generated for the memory access request, wherein the mapping circuit stores a plurality of segment descriptors, each segment descriptor associated with an N-dimensional array stored within the memory die;
determining whether the memory access request specifies a location in the local memory for the first processing tile, and
responsive to determining that the memory access request specifies the location in the local memory for the first processing tile, transmitting the memory access request from the first processing tile to the local memory provided by the at least one memory tile stacked with the first processing tile through conductive paths between the first processing tile and the local memory; or
responsive to determining that the memory access request does not specify the location in the local memory for the first processing tile, transmitting the memory access request from the first processing tile to a second processing tile of the plurality of processing tiles and through second conductive paths between the second processing tile and the local memory provided by the at least one memory tile stacked with the second processing tile.
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