US 12,223,195 B2
Memory controller and operating method thereof
Hyun Sub Kim, Seongnam (KR); Ie Ryung Park, Suwon (KR); Dong Sop Lee, Yongin (KR); and Sung Yeob Cho, Yongin (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on May 20, 2022, as Appl. No. 17/750,121.
Application 17/750,121 is a continuation in part of application No. 16/888,444, filed on May 29, 2020, granted, now 11,507,310.
Application 16/888,444 is a continuation in part of application No. 16/868,116, filed on May 6, 2020, granted, now 11,355,213, issued on Jun. 7, 2022.
Application 16/888,444 is a continuation in part of application No. 16/841,030, filed on Apr. 6, 2020, granted, now 11,264,086, issued on Mar. 1, 2022.
Application 16/888,444 is a continuation in part of application No. 16/730,826, filed on Dec. 30, 2019, granted, now 11,257,530, issued on Feb. 22, 2022.
Claims priority of application No. 10-2019-0108259 (KR), filed on Sep. 2, 2019; application No. 10-2019-0149055 (KR), filed on Nov. 19, 2019; and application No. 10-2020-0011548 (KR), filed on Jan. 31, 2020.
Prior Publication US 2022/0283725 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0647 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory device including a memory cell region for storing data, the memory device configured to loop back a first clock to generate a second clock and output read data that are read from the memory cell region in synchronization with the second clock; and
a memory controller configured to generate the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, for outputting the first clock to the memory device and for receiving the read data in response to the second clock.