US 12,223,184 B2
Distributed power up for a memory system
Giuseppe Cariello, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 5, 2022, as Appl. No. 17/737,539.
Prior Publication US 2023/0359370 A1, Nov. 9, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a set of memory devices; and
processing circuitry coupled with the set of memory devices and configured to cause the memory system to:
receive, from a host system, a command to initialize the set of memory devices included in the memory system;
select, based at least in part on the command, a first memory device from the set of memory devices using an output of a random number generator;
read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device;
perform a first initialization corresponding to the command on a first subset of the set of memory devices according to the first operational parameter, the first subset of the set of memory devices comprising the first memory device;
read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of a second subset of the set of memory devices different than the first subset of the set of memory devices;
perform, after performing the first initialization and reading the set of second operational parameters, a second initialization corresponding to the command on the second subset of the set of memory devices according to the set of second operational parameters; and
select, based at least in part on a second command to initialize the set of memory devices, a third memory device from the set of memory devices using a second output of the random number generator.