US 12,223,174 B2
Modulating credit allocations in memory subsystems
Nagaraj Ashok Putti, Bangalore (IN); Abhra Bagchi, Bangalore (IN); Vyagrheswarudu Durga Nainala, Bangalore (IN); and Venkateswaran Ananthanarayanan, Bangalore (IN)
Assigned to Google LLC, Mountain View, CA (US)
Appl. No. 18/250,476
Filed by Google LLC, Mountain View, CA (US)
PCT Filed Oct. 26, 2020, PCT No. PCT/US2020/057293
§ 371(c)(1), (2) Date Apr. 25, 2023,
PCT Pub. No. WO2022/093165, PCT Pub. Date May 5, 2022.
Prior Publication US 2024/0004551 A1, Jan. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory subsystem of a system on chip (SoC) comprising:
a memory controller operably connected to a credit controller, the memory controller comprising a buffer configured to store transaction requests, from one or more clients, to access data in one or more random-access memories (RAMs), the memory controller configured to:
monitor, for each client of the one or more clients, statistics of the transaction requests served by the memory controller, the statistics comprising at least two of a number of page hits in the one or more RAMs, a number of conflicts that require closing a page of the one or more RAMs before another page can be opened, or a respective number of credits allocated to the client;
determine, based on the statistics, whether memory throughput would be increased by increasing or decreasing the respective number of credits allocated to at least one client of the one or more clients; and
generate, based on a determination that the memory throughput would be increased, an output signal, the output signal configured to indicate to the credit controller that the respective number of credits allocated to the at least one client of the one or more clients should be increased or decreased.