US 12,223,165 B2
Multicore, multibank, fully concurrent coherence controller
Matthew David Pierson, Frisco, TX (US); Kai Chirca, Dallas, TX (US); and Timothy David Anderson, University Park, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 28, 2022, as Appl. No. 17/875,440.
Application 17/875,440 is a continuation of application No. 16/653,139, filed on Oct. 15, 2019, granted, now 11,422,938.
Claims priority of provisional application 62/745,842, filed on Oct. 15, 2018.
Prior Publication US 2022/0374357 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 12/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01); G06F 12/0855 (2016.01); G06F 12/0875 (2016.01); G06F 12/0891 (2016.01); G06F 12/10 (2016.01); G06F 12/1009 (2016.01); G06F 13/12 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); H03M 13/01 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01); H03M 13/27 (2006.01); G06F 12/0846 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/064 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 9/30101 (2013.01); G06F 9/30123 (2013.01); G06F 9/3897 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 12/0607 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0855 (2013.01); G06F 12/0857 (2013.01); G06F 12/0875 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 13/124 (2013.01); G06F 13/1642 (2013.01); G06F 13/1663 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); H03M 13/015 (2013.01); H03M 13/098 (2013.01); H03M 13/1575 (2013.01); H03M 13/276 (2013.01); H03M 13/2785 (2013.01); G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 12/0851 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/304 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a cache tag bank;
a snoop filter bank coupled to the cache tag bank;
a memory bank coupled to the cache tag bank; and
a controller coupled to the cache tag bank, the controller configured to:
receive a first read request that includes a first address tag;
apply the first address tag to the snoop filter bank to determine that a unique state is associated with the first address tag;
issue a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag;
if the first snoop request returns a first value, respond to the first read request with the first value; and
if the first snoop request does not return a value, retrieve a second value from the memory bank or from an external memory and respond to the first read request with the second value.