US 12,223,100 B2
Hardware protection of inline cryptographic processor
Amritpal S. Mundra, Allen, TX (US); and William C. Wallace, Richardson, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 4, 2023, as Appl. No. 18/480,815.
Application 18/480,815 is a continuation of application No. 14/305,713, filed on Jun. 16, 2014, granted, now 11,809,610.
Prior Publication US 2024/0028775 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/79 (2013.01); G06F 12/14 (2006.01); G06F 21/60 (2013.01); G06F 21/62 (2013.01)
CPC G06F 21/79 (2013.01) [G06F 12/1408 (2013.01); G06F 21/606 (2013.01); G06F 21/62 (2013.01); G06F 2221/2107 (2013.01); G06F 2221/2125 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A data encryption system comprising:
an encryption engine including a plurality of encryption cores, each configured to perform at least one of multiple types of cryptographic operations, including an encryption operation, a decryption operation, and a message authentication operation;
a memory interface configured to write encrypted data received from one or more of the plurality of encryption cores to a memory, and further configured to provide encrypted data received from the memory to one or more of the plurality of encryption cores;
a command buffer configured to associate each transaction of multiple transactions of the data encryption system with a corresponding response of multiple responses by the memory interface; and
a scheduler configured to determine that a command specifies one of the multiple types of cryptographic operations based on a mode of a region of the memory which is specified by an address of the command.