US 12,223,009 B2
Systems and methods for efficient matrix multiplication
Jack David Kendall, San Mateo, CA (US)
Assigned to Rain Neuromorphics Inc., San Francisco, CA (US)
Filed by Rain Neuromorphics Inc., San Francisco, CA (US)
Filed on Mar. 30, 2021, as Appl. No. 17/217,776.
Application 17/217,776 is a continuation of application No. 16/543,426, filed on Aug. 16, 2019, granted, now 10,990,651.
Application 16/543,426 is a continuation of application No. 16/376,169, filed on Apr. 5, 2019, granted, now 10,430,493, issued on Oct. 1, 2019.
Claims priority of provisional application 62/653,194, filed on Apr. 5, 2018.
Prior Publication US 2021/0216610 A1, Jul. 15, 2021
Int. Cl. G06F 17/16 (2006.01); G06N 3/065 (2023.01); G11C 13/00 (2006.01)
CPC G06F 17/16 (2013.01) [G06N 3/065 (2023.01); G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/19 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A system of sparse vector-matrix multiplication comprising:
a circuit layer;
a plurality of electrodes formed on the circuit layer; and
a plurality of non-volatile memory devices on and sparsely coupled with the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell, the conductive core having an axis and sides, wherein the plurality of electrodes and the plurality of non-volatile memory devices form a matrix of conductances, wherein the matrix of conductances, using a model, is adjusted to obtain an effective matrix of conductances, wherein the model implements a neural network technique, wherein the effective matrix of conductances represents a set of weights in a layer of a neural network of the model, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the circuit layer is configured to:
receive a first plurality of input signals;
write a second plurality of input signals on an input set of the plurality of electrodes, wherein the second plurality of input signals is multiplied by the effective matrix of conductances to obtain a first plurality of output signals;
read from an output set of the plurality of electrodes the first plurality of output signals, and
output a second plurality of output signals.