US 12,222,893 B2
Connectivity in coarse grained reconfigurable architecture
Bryan Hornung, Plano, TX (US); and Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 10, 2023, as Appl. No. 18/388,784.
Application 18/388,784 is a continuation of application No. 17/402,900, filed on Aug. 16, 2021, granted, now 11,841,823.
Prior Publication US 2024/0086355 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/78 (2006.01); G06F 7/498 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 15/173 (2006.01)
CPC G06F 15/7825 (2013.01) [G06F 7/4981 (2013.01); G06F 7/4983 (2013.01); G06F 13/1668 (2013.01); G06F 13/4068 (2013.01); G06F 15/17375 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first memory-compute tile of a first node of multiple memory-compute nodes of a compute fabric, wherein the first memory-compute tile comprises:
first tile inputs coupled to respective outputs of second and third memory-compute tiles of the first node;
first tile outputs coupled to respective inputs of the second and third memory-compute tiles of the first node; and
a passthrough channel configured to communicate information between the second and third memory-compute tiles.