US 12,222,892 B2
Routing data between processing units indentified by a sequentially ordered list of a packet prefix
Sean Gregory Gibb, Calgary (CA); and Saeed Fouladi Fard, Calgary (CA)
Assigned to Eidetic Communications Inc., Calgary (CA)
Filed by EIDETIC COMMUNICATIONS INC., Calgary (CA)
Filed on Jun. 16, 2022, as Appl. No. 17/842,129.
Claims priority of application No. PCT/CA2022/050724 (WO), filed on May 9, 2022.
Prior Publication US 2023/0359581 A1, Nov. 9, 2023
Int. Cl. G06F 15/163 (2006.01); G06F 9/38 (2018.01)
CPC G06F 15/163 (2013.01) [G06F 9/3877 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A data processing system for performing a sequence of data operations, comprising:
a plurality of data processing circuits each configured to perform a respective data operation;
a target central processing unit (CPU) configured to generate a current prefix, the current prefix including a current sequentially ordered list of the plurality of data processing circuits corresponding to the sequence of data operations;
an interconnect circuit that is separate from the target CPU, the interconnect circuit in communication with the plurality of data processing circuits and the target CPU, the interconnect circuit configured to:
receive from the target CPU the current prefix;
receive from an input data source a current data payload to be processed;
generate a current data packet by prepending the current prefix to the current data payload; and
sequentially send the current data packet to the plurality of data processing circuits by:
i) determining, based on a next entry in the current sequentially ordered list included in the current prefix of the current data packet, a one of the plurality of data processing circuits associated with the next entry;
ii) removing the next entry and an associated set of parameters from the current prefix to generate an updated prefix;
iii) replacing the current prefix with the updated prefix in the current data packet;
iv) sending the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list included in the current prefix, together with the associated set of parameters;
v) receiving from the one of the plurality of data processing circuits an updated data packet including the updated prefix and a processed data payload generated by the one of the plurality of data processing circuits using the current data payload and the associated set of parameters;
vi) in response to determining that a next entry in the updated prefix is associated with any of the plurality of data processing circuits, repeating steps i) to v) using the updated data packet as the current data packet with the updated prefix being the current prefix; and
vii) in response to determining that the next entry in the updated prefix is associated with a data destination, removing the next entry from the updated prefix in the updated data packet and sending the updated data packet with the next entry removed to the data destination;
wherein each of the plurality of data processing circuits is configured to:
receive the current data packet and the associated set of parameters from the interconnect circuit;
perform a data operation on the current data payload included in the current data packet to generate the processed data payload; and
send the updated data packet including the processed data payload and the updated prefix to the interconnect circuit;
wherein:
each entry in the current sequentially ordered list comprises an address of the one of the plurality of data processing circuits associated with that entry;
the plurality of data processing circuits comprise two or more data processing circuits configured to perform a same data operation;
a first address in the current sequentially ordered list is a virtual address associated with the same data operation; and
when the next entry in the current sequentially ordered list comprises the first address, the interconnect circuit being configured to send the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list comprises the interconnect circuit being configured to:
determine an available one of the two or more data processing circuits configured to perform the same data operation;
replace the first address in the next entry with an actual address of the available one of the two or more data processing circuits configured to perform the same data operation; and
send the current data packet that includes the actual address to the available one of the two or more data processing circuits.