US 12,222,885 B2
Method for transferring data between a first digital domain and a second digital domain, and corresponding system on a chip
Nicolas Saux, Aix-en-Provence (FR); Sebastien Metzger, Aix-en-Provence (FR); and Herve Cassagnes, Salon-de-Provence (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Apr. 11, 2023, as Appl. No. 18/133,214.
Claims priority of application No. 2203375 (FR), filed on Apr. 12, 2022.
Prior Publication US 2023/0325336 A1, Oct. 12, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 1/10 (2006.01); G06F 1/24 (2006.01)
CPC G06F 13/405 (2013.01) [G06F 1/10 (2013.01); G06F 1/24 (2013.01); G06F 2213/0038 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system on a chip, comprising:
a first digital domain configured to be reinitialized by a first reinitialization signal;
a second digital domain; and
an interface circuit including at least one transfer element in the first digital domain;
wherein the interface circuit is configured to transfer data from said at least one transfer element to the second digital domain; and
wherein said at least one transfer element is configured to not be reinitialized by the first reinitialization signal;
wherein the interface circuit includes a signal adaptation element, out of said at least one transfer element, configured to transfer, between the first digital domain and the second digital domain, a link establishment conditioning signal; and
wherein said at least one signal adaptation element includes a starting register configured to input the value of the link establishment conditioning signal in a single cycle of a first clock signal and then preserve said value.