| CPC G06F 13/1673 (2013.01) [G06F 12/00 (2013.01); G06F 13/00 (2013.01); G06F 13/4243 (2013.01); G06F 13/4282 (2013.01); G11C 5/04 (2013.01); G11C 7/1072 (2013.01); G11C 15/00 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |
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1. A memory module operable in a computer system, the computer system including a memory controller coupled to a memory bus, the memory bus including address and control signal lines and data signal lines, the memory module comprising:
a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system to provide electrical connections between the memory bus and components of the memory module mounted on the printed circuit board;
logic coupled to the printed circuit board and configurable to receive input address and control signals associated with a read or write memory command via the address and control signal lines and to output registered address and control signals corresponding to the input address and control signals, the input address and control signals including a plurality of input chip select signals and other input address and control signals, the plurality of input chip select signals at least including a first input chip select signal and a second input chip select signal, the first input chip select signal having an active value and the second input chip select signal having an inactive value, the registered address and control signals including a plurality of registered chip select signals and other registered address and control signals, the plurality of registered chip select signals at least including a first registered chip select signal corresponding to the first input chip select signal and a second registered chip select signal corresponding to the second input chip select signal, the first registered chip select signal having an active value and the second registered chip select signal having an inactive value, wherein the logic is further configurable to output data transfer control signals associated with the read or write memory command;
memory devices mounted on the printed circuit board, the memory devices at least including first memory devices and second memory devices, wherein the first memory devices are configured to receive the first registered chip select signal and the other registered address and control signals, and to receive or output data signals associated with the read or write command via memory device data signal lines on the printed circuit board, the memory device data signal lines corresponding, respectively, to the data signal lines in the memory bus, and wherein the second memory devices are configured to receive the second registered chip select signal and the other registered address and control signals; and
circuitry coupled between the memory devices and the data signal lines in the memory bus, and configurable to be in any of a plurality of states including a first state and a second state, wherein:
the circuitry is configurable to transition from the first state to the second state in response to the data transfer control signals;
the circuitry in the first state is configured to disable signal communication through the circuitry;
the circuitry in the second state is configured to transfer the data signals associated with the read or write command between the memory device data signal lines and the data signal lines in the memory bus via registered data transfers in accordance with a transfer time budget of the memory module, the data signals including respective sets of consecutively transmitted data bits corresponding to respective data signal lines in the memory bus, each respective set of consecutively transmitted data bits being successively transferred through the circuitry between a respective data signal line in the memory bus and a corresponding one of the memory device data signal lines;
the transfer time budget of the memory module includes a predetermined amount of time delay associated with the registered data transfers through the circuitry; and
an overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the memory devices by at least the predetermined amount of time delay.
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