US 12,222,869 B2
Memory access control through permissions specified in page table entries for execution domains
Steven Jeffrey Wallach, Dallas, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,366.
Application 17/899,366 is a continuation of application No. 17/158,979, filed on Jan. 26, 2021, granted, now 11,436,156.
Application 17/158,979 is a continuation of application No. 16/520,292, filed on Jul. 23, 2019, granted, now 10,915,457, issued on Feb. 9, 2021.
Claims priority of provisional application 62/724,896, filed on Aug. 30, 2018.
Prior Publication US 2022/0414019 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 9/455 (2018.01); G06F 12/1009 (2016.01); G06F 12/14 (2006.01); G11C 8/20 (2006.01); G11C 11/16 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 9/45533 (2013.01); G06F 12/1441 (2013.01); G11C 8/20 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1695 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a page table having a plurality of page table entries, including a first page table entry configured to specify:
a base to map a virtual memory address region to a physical memory address region; and
a list of permissions for a plurality of domains of routines respectively; and
a logic circuit configured to, in response to an instruction of a routine executed in a processor to access a virtual memory address in a virtual memory address region:
determine, based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region; and
control, based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region.