US 12,222,868 B2
Processor and operating method for a homogeneous dual computing system
Yingbing Guan, Shanghai (CN); Zhenhua Huang, Beijing (CN); Yanting Li, Beijing (CN); and Yipu Liu, Shanghai (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Sep. 15, 2023, as Appl. No. 18/467,901.
Claims priority of application No. 202211490770.X (CN), filed on Nov. 25, 2022.
Prior Publication US 2024/0176746 A1, May 30, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/084 (2016.01); G06F 12/0891 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/084 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor for building a homogeneous dual computing system, comprising:
a trusted core, having an access right to an isolated storage space of a system memory;
a normal core, which is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space; and
a shared cache, shared by the trusted core and the normal core;
wherein:
in response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from a first cache write-back instruction, according to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed; and
wherein instead of responding to the cache flush instruction issued by the normal core as the second cache write-back instruction, the first cache write-back instruction is called to write all cache lines of the shared cache back to the system memory.