US 12,222,867 B2
Processor, computer system, and method for flushing hierarchical cache structure based on a designated key identification code and a designated address
Weilin Wang, Beijing (CN); Yingbing Guan, Shanghai (CN); and Minfang Zhu, Shanghai (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Oct. 14, 2022, as Appl. No. 18/046,642.
Claims priority of application No. 202111374225.X (CN), filed on Nov. 19, 2021.
Prior Publication US 2023/0161709 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 21/60 (2013.01)
CPC G06F 12/0891 (2013.01) [G06F 21/602 (2013.01); G06F 2212/1052 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A computer system, flushing a hierarchical cache structure based on a designated key identification code and a designated address, comprising:
a first processor fabricated on a first die, comprising a first core, wherein the first core comprises a decoder, a memory ordering buffer, and a first in-core cache module; and
a first last-level cache, fabricated in the first processor;
wherein:
in response to an instruction of an instruction set architecture that is provided to flush the hierarchical cache structure based on the designated key identification code and the designated address, the decoder outputs at least one microinstruction;
according to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then is provided to the first last-level cache by the first in-core cache module;
in response to the flushing request, the first last-level cache searches the first last-level cache for a matching cache line that matches the designated key identification code and the designated address, and flushes the matching cache line.