US 12,222,855 B2
Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device
Do Hun Kim, Icheon (KR); Ju Hyun Kim, Icheon (KR); and Jin Yeong Kim, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Dec. 29, 2022, as Appl. No. 18/148,149.
Application 18/148,149 is a continuation of application No. 17/104,973, filed on Nov. 25, 2020, granted, now 11,573,891.
Claims priority of application No. 10-2019-0152195 (KR), filed on Nov. 25, 2019; application No. 10-2020-0061130 (KR), filed on May 21, 2020; and application No. 10-2020-0083485 (KR), filed on Jul. 7, 2020.
Prior Publication US 2023/0139864 A1, May 4, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0292 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 13/1605 (2013.01); G06F 13/1668 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a main memory configured to store data;
a processor configured to generate commands for accessing the main memory;
a scheduling circuit configured to receive the commands, re-order the commands based on each addresses of the main memory corresponding to the commands, and output a first command among the commands; and
a filtering circuit configured to provide the first command to the main memory based on whether a first address corresponding to the first command is included in address information including an address corresponding to a command for which an operation completion response is not received from the main memory.