US 12,222,806 B2
Cache line data protection
Marco Sforzin, Cernusco sul Naviglio (IT); and Paolo Amato, Treviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 28, 2023, as Appl. No. 18/215,588.
Claims priority of provisional application 63/357,508, filed on Jun. 30, 2022.
Prior Publication US 2024/0004759 A1, Jan. 4, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 12/0868 (2016.01); H04L 67/568 (2022.01)
CPC G06F 11/1076 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0689 (2013.01); G06F 11/1048 (2013.01); G06F 12/0868 (2013.01); G06F 2211/1009 (2013.01); G06F 2211/109 (2013.01); G06F 2212/262 (2013.01); G06F 2212/282 (2013.01); G06F 2212/403 (2013.01); H04L 67/568 (2022.05)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a number of memory devices; and
a memory controller coupled to the number of memory devices, the memory controller configured to:
receive a plurality of user data blocks (UDBs) corresponding to a cache line and belonging to different stripes, wherein the plurality of UDBs corresponding to the cache line is a data transfer unit to or from a cache;
generate error detection information based collectively on the plurality of UDBs corresponding to the cache line;
generate error correction information based collectively on the plurality of UDBs corresponding to the cache line; and
write, along with the error detection information and error correction information, the plurality of UDBs to the number of memory devices;
read the plurality of UDBs; and
in response to the plurality of UDBs being indicated as containing one or more errors:
perform one second error correction operation on a first subset of the plurality of UDBs using a first parity data block; and
perform, independently of the one second error correction operation, another second error correction operation on a second subset of the plurality of UDBs using a second parity data block.