US 12,222,797 B2
Dynamic configuration of processor sub-components
James Mossman, Austin, TX (US); Robert Cohen, Austin, TX (US); Sudherssen Kalaiselvan, Santa Clara, CA (US); and Tzu-Wei Lin, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 19, 2022, as Appl. No. 18/084,499.
Prior Publication US 2024/0201777 A1, Jun. 20, 2024
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3287 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
observing, using a control circuit coupled to a target sub-component of a functional unit of a processor, a utilization of the target sub-component, wherein the target sub-component corresponds to one of a plurality of pipelines executing in parallel;
detecting that the utilization is outside a desired utilization range; and
throttling at least one sub-component of the functional unit to shut off the one of the plurality of pipelines.