US 12,222,750 B2
Timestamp alignment across multiple computing nodes
Mark Bordogna, Andover, MA (US); and Jonathan A. Robinson, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 16, 2023, as Appl. No. 18/198,150.
Application 18/198,150 is a continuation of application No. 16/726,684, filed on Dec. 24, 2019, granted, now 11,693,448.
Claims priority of provisional application 62/814,203, filed on Mar. 5, 2019.
Prior Publication US 2023/0367362 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/14 (2006.01); G06F 1/12 (2006.01); G06F 9/54 (2006.01); H04L 43/106 (2022.01)
CPC G06F 1/14 (2013.01) [G06F 1/12 (2013.01); G06F 9/542 (2013.01); H04L 43/106 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a network interface device comprising:
a first interface to a first processor and
circuitry to receive a time stamp from the first processor by the first interface, wherein:
receipt of the time stamp from the first processor by the first interface is to cause the circuitry to provide, to the first processor, a time stamp value based on a clock signal from a clock source corresponding to the received time stamp from the first processor and
the first processor is to adjust a time stamp counter value based, at least in part, on the time stamp value based on the clock signal corresponding to the received time stamp from the first processor.