US 12,222,748 B2
Clock generating circuit
Ghia-Ming Hong, Tainan (TW); Zheng-Zhi Huang, Tainan (TW); Puo-Tsang Huang, Tainan (TW); Ya-Sen Chang, Tainan (TW); and Chen-Cheng-Hung Hung, Tainan (TW)
Assigned to Himax Imaging Limited, Tainan (TW)
Filed by Himax Imaging Limited, Tainan (TW)
Filed on Apr. 6, 2023, as Appl. No. 18/131,845.
Prior Publication US 2024/0338052 A1, Oct. 10, 2024
Int. Cl. G06F 1/10 (2006.01)
CPC G06F 1/10 (2013.01) 3 Claims
OG exemplary drawing
 
1. A clock generating circuit, comprising:
an input terminal, configured to receive a clock signal;
an output terminal, configured to output an output signal;
a gray counter circuit, coupled to the input terminal, and configured to divide the clock signal to produce a first output signal, wherein the first output signal is a gray code; and
a shielding circuit, coupled to the input terminal, the gray counter circuit and the output terminal, and configured to shield a glitch in the first output signal to generate the output signal according to the clock signal;
wherein the gray counter circuit comprises:
a ripple counter circuit, configured to output a first data output signal and a second data output signal according to the clock signal; and
an encoder circuit, coupled to the ripple counter circuit, and configured to output the first output signal according to the first data output signal and the second data output signal;
wherein the ripple counter circuit comprises:
a first D-flip flop circuit, comprising a first clock input terminal, a first data input terminal, a first data output terminal and a first inverted data output terminal; and
a second D-flip flop circuit, comprising a second clock input terminal, a second data input terminal, a second data output terminal and a second inverted data output terminal;
wherein the first clock input terminal is configured to receive the clock signal, the first data output terminal is coupled to the second clock input terminal and configured to output the first data output signal, the second data output terminal is configured to output the second data output signal, the first data input terminal is coupled to the first inverted data output terminal, and the second data input terminal is coupled to the second inverted data output terminal.