US 12,222,619 B2
Display panel and display device
Qiujie Su, Beijing (CN); Xiaoyuan Wang, Beijing (CN); Zhihua Sun, Beijing (CN); Li Tian, Beijing (CN); Seungmin Lee, Beijing (CN); and Jiantao Liu, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/636,148
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Mar. 10, 2021, PCT No. PCT/CN2021/079911
§ 371(c)(1), (2) Date Feb. 17, 2022,
PCT Pub. No. WO2021/208643, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 202010291154.6 (CN), filed on Apr. 14, 2020.
Prior Publication US 2022/0291558 A1, Sep. 15, 2022
Int. Cl. G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/1339 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC G02F 1/136286 (2013.01) [G02F 1/133514 (2013.01); G02F 1/1339 (2013.01); G02F 1/136222 (2021.01); G02F 1/1368 (2013.01); H01L 27/124 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
an array substrate, wherein the array substrate comprises a first substrate, gate lines, data lines, and a plurality of sub-pixel units, the first substrate has a plurality of sub-pixel regions arranged in an array, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions, the first wiring regions intersect with the second wiring regions;
wherein at least part of each of the sub-pixel units is located on one of the sub-pixel regions, the gate lines are located on the first wiring regions and are electrically connected with the sub-pixel units, the data lines are located on the second wiring regions and are electrically connected with the sub-pixel units, the data lines and the gate lines are insulated from each other and orthographic projections of the data line and the gate line on the first substrate intersect with each other, the data line has an alignment part, and an orthographic projection of the alignment part on the first substrate is located in a region where the first wiring region and the second wiring region intersect, wherein the data line further has main line parts located on opposite sides of the alignment part in a column direction, the data line further has a transition part located between the main line part and the alignment part, and a size of the transition part in a row direction is larger than that of the main line part in the row direction and smaller than that of the alignment part in the row direction; and
a spacer disposed on a side of the alignment part away from the array substrate, wherein an orthographic projection of the spacer on the first substrate is located within an orthographic projection of the alignment part on the first substrate,
wherein barrier walls located on opposite sides of the spacer in the column direction are further provided on the first substrate, and a distance between the barrier wall and the spacer is a second distance between 15 μm and 40 μm, and
wherein the first wiring area is further provided with a common line, and an overlapping portion of orthographic projections of the transition part and the common line on the first substrate forms another barrier wall.